System Hardware Composition
Each high-speed transceiver consists of two channels: a transmitter and a receiver. The transmitter and receiver are composed of a physical coding sublayer (PCS, P-field Si-Cal Coding Sublayer) and a physical media additional sublayer (PMA, Physic-Cal Media Additional Sublayer).
PCS includes the core logic implementation of digital functions in the transceiver compatible with the supported protocol, and the transmission channel includes phase compensation FIFO, byte serializer, 8B/10B encoder and other modules. Receiving channels include word aligner, rate matching FIFO, 8B/10B decoder, byte unstring, byte sorter, phase compensation FIFO and other modules.
PMA includes an analog circuit for I/O buffers, a CDR, SER/DES and a programmable pre-weighting and equalization for optimizing the performance of a serial data channel.
When the device transceiver channel works, the output parallel data in the FPGA architecture is transmitted through the transmitter PCS and PMA, and finally converted into serial data to be sent out. The received input serial data is processed by the receiver PMA and PCS in serial data format and transmitted to the internal FP architecture for further processing.
The FPGA integration
High speed transceivers are widely used. Taking SATA interface solid-state disk based on FPGA as an example, SATA interface solid-state disk is the development of the future trend, while high speed serial transceivers realize the IP core storage mode of SATA, and high speed transceivers are the key components of physical layer implementation of SATA protocol. SATA protocol serial data works at a transmission rate of 1.5-6Gbit/s, which cannot be directly realized by FPGA. In order to meet this demand, many FPGA manufacturers integrate general purpose high-speed physical devices inside FPGA, and provide flexible configuration mode to accomplish many similar functions.
